1. Field
This disclosure relates generally to single-event latch-up and, more specifically, to techniques for preventing single-event latch-up of a semiconductor device.
2. Related Art
A single-event upset (SEU) is a change of state caused by ions or electromagnetic radiation striking a sensitive node in a semiconductor device, such as a node in a microprocessor, memory, or power transistor. In general, the state change is a result of free charge created by ionization in or close to a sensitive node of a logic element (e.g., a node of a memory bit cell). The error in semiconductor device output or operation due to a high energy particle strike is often referred to as a soft error upset or SEU.
Typically, an SEU has not permanently damaged functionality of a semiconductor device. In contrast, a single-event latch-up (SEL), a single-event gate rupture (SEGR), and/or a single-event burnout (SEB) may permanently damage a semiconductor device. An SEL may, for example, be attributed to parasitic circuit elements that form a silicon-controlled rectifier (SCR) in a semiconductor device. During an SEL, an SEL induced current may destroy components of a semiconductor device if the SEL induced current is not limited and promptly removed. In general, removal of power to a semiconductor device has been required in response to all non-catastrophic SEL events, in order to recover operations of the semiconductor device.
Terrestrial SEUs may occur due to cosmic particles colliding with atoms in the atmosphere, creating cascades or showers of neutrons and protons, which in turn may interact with circuits of a semiconductor device. At sub-micron geometries, SEUs may adversely affect semiconductor devices in the atmosphere. In space, high energy particles exist as part of the natural background. Solar particle events and high energy protons trapped in the magnetosphere of the Earth may also lead to SEUs. Secondary atmospheric neutrons generated by cosmic rays can also reach energy levels that are capable of producing SELs in avionic electronics on flights over the poles or at high altitude. Trace amounts of radioactive elements in integrated circuit (chip) packages may also cause SELs. In order to prevent latch-up in space applications, electronic devices may employ epitaxial substrate, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS) technologies to reduce or eliminate SEL susceptibility, albeit at increased cost.
In semiconductor devices that utilize complementary metal-oxide semiconductor (CMOS) technology there are a number of parasitic npn and pnp bipolar junction transistors (BJTs) that may be formed from the combination of source/drain regions, n-type wells, p-type wells, and substrates utilized in CMOS technology. The parasitic BJT devices may create problems when triggered. For example, triggering the parasitic BJT devices may lead to shorting power (VDD) and ground (VSS) lines, which may result in destruction of an associated chip or an associated electronic system failure that can only be resolved by power-down.